This invention relates to phase locked loop (PLL) circuits and, in particular, to PLL circuits exhibiting little jitter and enhanced bandwidths.
A problem resolved by the invention may be better explained by reference to FIGS. 1 and 2, which show a known prior art PLL circuit. FIG. 1 is a block diagram of a prior art PLL circuit which includes a crystal oscillator 11 for generating a low noise reference frequency clock signal (fre.sub.f). The fre.sub.f is supplied to one input of a phase detector 15 having a second input to which is supplied an output (f.sub.o /N) of a divide-by-N circuit 16. The output of the phase detector 15 supplies an up-count or a down-count signal to a charge pump circuit 17. Charge pump circuit 17 then supplies a current output to a filter network 19 whose output (in the form of a control voltage) is supplied to an input of a voltage controlled oscillator (VCO) 21, which produces an output clock signal, f.sub.o, having a frequency which is equal to (N)(f.sub.ref). The f.sub.o signal is supplied to divide-by-N network 16 to produce a feedback signal equal to f.sub.o /N which is supplied to the phase detector 15.
Noise (n.sub.ref) associated with the reference frequency (f.sub.ref) is injected into the front end of the system and is represented in FIG. 1 by block 13 which is part of the input to the phase detector 15. There is also noise (n.sub.vco) associated with VCO 21 which is injected into the output of the PLL system. The noise injected into the system by VCO 21 is illustrated in FIG. 1 as an n.sub.vco input in block 23. Typically, n.sub.vco is much greater than n.sub.ref and is the leading cause of jitter at the PLL output. It is an object of the invention to reduce the noise and jitter present at the PLL output.
When the VCO noise dominates, it is known that the output noise associated with the VCO (and hence, f.sub.o) can be reduced by increasing the bandwidth of the PLL (also referred to hereinafter as the PLL bandwidth or (.omega..sub.BW). For stability reasons, there is an upper limit placed on .omega..sub.BW. A common rule of thumb is to select the PLL bandwidth such that .omega..sub.BW /f.sub.ref &lt;2 .pi./10.
However, there is a problem in trying to increase the bandwidth which is better explained with reference to the semi-schematic, semi-block diagram of FIG. 2. The charge pump circuit 17 includes a reference current source I.sub.ref which is mirrored via a mirror amplifier (comprising transistors Tr, T1 and P1) to produce a pull up current, Ipu (via a mirror transistor P3), or a pull down current, Ipd (via mirroring transistors P2, T2 and T3). The bandwidth (.omega..sub.BW) for a PLL having a charge pump circuit 17 of the type shown in FIG. 2 may be expressed as follows: EQU .omega..sub.BW =[(Kvco)(Ip)R]/N eq. 1
Where:
a) Kvco is the control voltage (V.sub.CTL) to output frequency (f.sub.o) transfer constant of the VCO (e.g., Kvco=f.sub.o /V.sub.CTL of VCO21 as shown in FIG. 2); PA1 b) Ip is the charge pump current produced at the output of charge pump 17 which flows into or out of the filter network 19; PA1 c) N is the division ratio of the feedback divider network 16; and PA1 d) R is the resistance of filter network 19.
The filter network also includes an integrating capacitor C. However, C is generally neglected in the discussion to follow.
As is evident from eq. 1, the bandwidth (.omega..sub.BW) of the PLL is a function of "N" and, since it is inversely proportional to N, .omega..sub.BW decreases as N increases. However, N is normally set by the user after the PLL has been designed. Thus, for all but the smallest values of N, the PLL will be operating in a suboptimal condition producing an output noise which is larger than necessary. That is, the greater N is made, the lower .omega..sub.BW is going to be; and, as a result of .omega..sub.BW being decreased, more of the output noise (n.sub.vco) will pass to the output of the PLL.
However, in many applications, the division ratio "N" can not be set to an optimum value because in those applications the division ratio "N" is varied during the operation of the system. For example, in microprocessor systems, power reduction is often achieved by reducing the divider ratio N which causes a corresponding reduction in the clock frequency supplied to the system. In other applications, such as a wireless communication system, the divider ratio N is changed during run-time. That is, a user may switch between different frequency bands or different channels by changing the value of "N" during run-time. In still other applications such as a standard cell PLL, the division ratio "N" may be varied by different users resulting, for many applications, in a decrease in the bandwidth with an attendant increase in the output noise and jitter of the VCO output supplied to the system.